module CPU (
	input clk,    // Clock
	input clk_en, // Clock Enable
	input rst_n,  // Asynchronous reset active low
	input [31:0] instruction
	
);

	reg [31:0] instruction_if_id;
	reg [31:0] instruction_id_exe;
	reg [31:0] instruction_exe_mem;
	reg [31:0] instruction_mem_wb;

	// Stage 1
	always @(posedge clk) begin
		instruction_if_id <= instruction;
	end

	// Stage 2
	always @(posedge clk) begin
		instruction_id_exe <= instruction_if_id;
	end

	// Stage 3
	always @(posedge clk) begin
		instruction_exe_mem <= instruction_id_exe;
	end

	// Stage 4
	always @(posedge clk) begin
		instruction_mem_wb <= instruction_exe_mem;
	end

	// Stage 5
	always @(posedge clk) begin
		
	end

endmodule